Multivariate cryptography based on clipped hopfield neural network

ABSTRACT

The systems and methods disclosed herein, in one aspect thereof, can encrypt and decrypt messages using a multivariate extended Clipped Hopfield neural network that uses a Diffie-Hellman like key exchange algorithm. The proposed cryptosystem comprises three stages that are involved in the communication. A first stage, where parameters are initialized and private keys are generated, a second stage where various base matrix pairs and threshold vectors are synchronized between the sender and the recipient, and a third stage, where encryption/decryption is performed.

TECHNICAL FIELD

This disclosure generally relates to a multivariate public key cryptosystem that uses an extended Clipped Hopfield neural networks and related embodiments.

BACKGROUND

Security issues in electronic communications have been very important in the information age. Public key cryptographies (PKC) such as RSA and ECC (elliptic curve cryptosystems) have been adopted as key components for internet security, and in particular, for e-commerce systems authentication (electronic signatures) and secure communications. The RSA and ECC are mainly constructed from the complexity of integer factorization and discrete logarithm respectively. Although no proof is known for their NP-completeness or NP-hardness, both cryptosystems are still believed to be hard to break using convention systems. However, quantum computers have re-defined what problems are computational tractable and intractable, which has posed a new challenge to the security of classical cryptosystems.

The above-described background is merely intended to provide an overview of contextual information regarding networks, and is not intended to be exhaustive. Additional context may become apparent upon review of one or more of the various non-limiting embodiments of the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

Numerous aspects and embodiments are set forth in the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

FIG. 1 is an example non-limiting schematic diagram of a model of a neuron according to an aspect or embodiment of the subject disclosure;

FIG. 2 is an example non-limiting schematic diagram of a cryptosystem flow according to an aspect or embodiment of the subject disclosure;

FIG. 3 is an example non-limiting graph showing sensitivity to plaintext and key for data traversing a cryptosystem according to an aspect or embodiment of the subject disclosure;

FIG. 4 is an example non-limiting graph showing sensitivity to plaintext and key for data traversing a cryptosystem according to an aspect or embodiment of the subject disclosure;

FIG. 5 is an example non-limiting graph showing sensitivity to plaintext and key for data traversing a cryptosystem according to an aspect or embodiment of the subject disclosure;

FIG. 6 is an example non-limiting graph showing sensitivity to plaintext and key for data traversing a cryptosystem according to an aspect or embodiment of the subject disclosure;

FIG. 7 is an example non-limiting process flow diagram of a cryptosystem method according to an aspect or embodiment of the subject disclosure;

FIG. 8 is an example non-limiting process flow diagram of a cryptosystem method according to an aspect or embodiment of the subject disclosure;

FIG. 9 illustrates an example schematic block diagram of a computing environment in accordance various aspects of this disclosure; and

FIG. 10 illustrates a block diagram of a computer operable to execute the disclosed communication architecture.

DETAILED DESCRIPTION

Various aspects or features of this disclosure are described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In this specification, numerous specific details are set forth in order to provide a thorough understanding of this disclosure. It should be understood, however, that the certain aspects of disclosure may be practiced without these specific details, or with other methods, components, molecules, etc. In other instances, well-known structures and devices are shown in block diagram form to facilitate description and illustration of the various embodiments. Additionally, elements in the drawing figures are not necessarily drawn to scale; some areas or elements may be expanded to help improve understanding of certain aspects or embodiments.

The terms “access point,” “server,” “base server,” (BS) and the like, are utilized interchangeably in the subject application, and refer to a network component or appliance that serves and receives data, control, voice, video, sound, gaming, or substantially any data-stream or signaling-stream from a set of subscriber stations. Data and signaling streams can be packetized or frame-based flows. Furthermore, the terms “user,” “subscriber,” “customer,” “consumer,” and the like are employed interchangeably throughout the subject specification, unless context warrants particular distinction(s) among the terms. It should be noted that such terms can refer to human entities or automated components supported through artificial intelligence (e.g., a capacity to make inferences based on complex mathematical formalisms), which can provide simulated vision, sound recognition and so forth.

It is noted that, terms “user equipment,” “device,” “user equipment device,” “client,” and the like are utilized interchangeably in the subject application, unless context warrants particular distinction(s) among the terms. Such terms can refer to network component(s) or appliance(s) that servers and receives data, voice, video, sound, games, or substantially any data-stream or signaling-stream to or from network components and/or other devices. By way of example, a user equipment device and the like, as used herein and throughout this disclosure, can comprise a mobile device such as an electronic device capable of wirelessly sending and receiving data. A user equipment device may have a processor, a memory, a transceiver, an input, and an output. Examples of such devices include cellular telephones, personal digital assistants, portable computers, tablet computers, handheld gaming consoles, etc. The memory stores applications, software, or logic. Examples of processors are computer processors (processing units), microprocessors, digital signal processors, controllers and microcontrollers, etc. Examples of device memories that may comprise logic include RAM (random access memory), flash memories, ROMS (read-only memories), EPROMS (erasable programmable read-only memories), and EEPROMS (electrically erasable programmable read-only memories).

Furthermore, the terms “real-time,” “near real-time,” “dynamically,” “instantaneous,” “continuously,” and the like are employed interchangeably or similarly throughout the subject specification, unless context warrants particular distinction(s) among the terms. It should be noted that such terms can refer to data which is collected and processed at an order without perceivable delay for a given context, the timeliness of data or information that has been delayed only by the time required for electronic communication, actual or near actual time during which a process or event occur, and temporally present conditions as measured by real-time software, real-time systems, and/or high-performance computing systems. Real-time software and/or performance can be employed via synchronous or non-synchronous programming languages, real-time operating systems, and real-time networks, each of which provide frameworks on which to build a real-time software application. A real-time system may be one where its application can be considered (within context) to be a main priority. In a real-time process, the analyzed (input) and generated (output) samples can be processed (or generated) continuously at the same time (or near the same time) it takes to input and output the same set of samples independent of any processing delay.

Aspects or features of the subject specification can be exploited in substantially any radio access network employing respective radio access technologies, e.g., Wi-Fi, global system for mobile communications, universal mobile telecommunications system, worldwide interoperability for microwave access, enhanced general packet radio service, third generation partnership project long term evolution, fourth generation long term evolution, third generation partnership project 2, ultra mobile broadband, high speed packet access, Zigbee, X^(th) generation, long term evolution, or another IEEE 802.XX technology. Additionally, substantially all aspects of the subject specification can be exploited in legacy telecommunication technologies.

The systems and methods disclosed herein, in one aspect thereof, can encrypt and decrypt messages using a multivariate extended Clipped Hopfield neural network that uses a Diffie-Hellman like key exchange algorithm. The proposed cryptosystem comprises three stages that are involved in the communication. A first stage, where parameters are initialized and private keys are generated, a second stage where various base matrix pairs and threshold vectors are synchronized between the sender and the recipient, and a third stage, where encryption/decryption is performed. Initialization and synchronization can be done only once before the first communication of two parties. In order to obtain higher security, the iteration time ρ can be kept as a variable for different sessions.

“Logic” as used herein and throughout this disclosure, refers to any information having the form of instruction signals and/or data that may be applied to direct the operation of a processor. Logic may be formed from signals stored in a memory device. Software is one example of such logic. Logic may also be comprised by digital and/or analog hardware circuits, for example, hardware circuits comprising logical AND, OR, XOR, NAND, NOR, and other logical operations. Logic may be formed from combinations of software and hardware. On a network, logic may be programmed on a server, or a complex of servers. A particular logic unit is not limited to a single logical location on the network.

It is noted that user equipment devices can communicate with each other and with other elements via a network, for instance, a wireless network, or a wireline network. A “network” can include broadband wide-area networks such as cellular networks, local-area networks, wireless local-area networks (e.g., Wi-Fi), and personal area networks, such as near-field communication networks including BLUETOOTH®. Communication across a network is preferably packet-based; however, radio and frequency/amplitude modulations networks can enable communication between communication devices using appropriate analog-digital-analog converters and other elements. Communication is enabled by hardware elements called “transceivers.” User equipment devices can have more than one transceiver, capable of communicating over different networks. For example, a cellular telephone can include a cellular transceiver for communicating with a cellular base station, a Wi-Fi transceiver for communicating with a Wi-Fi network, and a BLUETOOTH® transceiver for communicating with a BLUETOOTH® device. A Wi-Fi network is accessible via “access points” such as wireless routers, etc., that communicate with the Wi-Fi transceiver to send and receive data. The Wi-Fi network can further be connected to the internet or other packet-based networks. The “bandwidth” of a network connection or an access point is a measure of the rate of data transfer, and can be expressed as a quantity of data transferred per unit of time. Additionally, communication (e.g., voice and/or data traffic) between one or more components can include, wired communications (routed through a backhaul broadband wired network, an optical fiber backbone, twisted-pair line, T1/E1 phone line, digital subscriber line, coaxial cable, and/or the like), and or radio broadcasts (e.g., cellular channels, Wi-Fi channels, satellite channels, and/or the like).

A network, as used herein, typically includes a plurality of elements that host logic for performing tasks on the network. The logic can be hosted on servers. In modern packet-based wide-area networks, servers may be placed at several logical points on the network. Servers may further be in communication with databases and can enable communication devices to access the contents of a database. Billing servers, application servers, etc. are examples of such servers. A server can include several network elements, including other servers, and can be logically situation anywhere on a service provider's network, such as the back-end of a cellular network.

Various embodiments disclosed herein include a system that has a processor and a memory that stores executable instructions, that when executed by the processor facilitate performance of operations. The operations include initializing a system parameter. The operations also include randomly generating a private key based on Diffie-Hellman key exchange with a message recipient device. The operations also include generating a base matrix pair as a function of the private key that is synchronized with another base matrix pair of the message recipient device and determining a threshold vector using the system parameter and the private key resulting in a synchronized threshold vector with the message recipient device. The operations can also include encrypting a communication based on the synchronized threshold vector and the synchronized base matrix pair.

In another embodiment, a method includes determining, by a system comprising a processor, a set of system parameters. The method can also comprise generating a random private key based on a Diffie-Hellman key exchange program with a device associated with a message recipient and generating a base matrix pair as a function of the private key that is synchronized with another base matrix pair of the message recipient. The method can also comprise synchronizing a threshold vector with another threshold vector of the message recipient using a system parameter of the set of system parameters and the private key and encrypting a communication using the threshold vector and the synchronized base matrix pair.

In another embodiment, a system can be provided that has a processor and a memory that stores executable instructions, that when executed by the processor facilitate performance of operations. The operations include initializing a system parameter. The operations also include randomly generating a private key based on a Diffie-Hellman key exchange with a sending device. The operations also include generating a base matrix pair as a function of the private keys, wherein the base matrix pair is synchronized with the sending device and determining a threshold vector using the system parameter and the private key. The operations can also include a received message based on the threshold vector and the base matrix pair.

Multivariate crypytography (“MVC”) is a kind of post-quantum cryptography algorithm where a one-way function takes the form of a set of quadratic polynomials. The scheme evolves from the idea of univariate modular equation y=x^(e) mod p in RSA by either 1) replacing it with a small/moderate set of modular equations of low degree modulo a large number or 2) replacing a large set of modular equations of low degree modulo a small number. It starts from a set of quadratic equations, with some specific structure, e.g., Y=F(X); Y=(y₁, . . . , y_(k)); X=(x₁, . . . , x_(m)); and hides the underlying structure manipulated by two linear (or affine) bijections matrices T, S. The public key is obtained by combing F, T and 5, say φ=T∘F∘S and makes the solution of quadratic polynomials exits. For PKC, the encryption can use 0=T∘F∘s and the decryption involves solving the easy equations by means of known 5, T. Typically, the easy equations can be in the form of y₁=x₁x₂ mod p, where p is an RSA integer; y_(i−1)=x_(i)λ_(i)(x₁, . . . , x_(i−1))+κ_(i)(x₁, . . . , x_(i−1)) for i=3, . . . , k+1 where λ_(i) is linear; κ_(i) is quadratic; and there is k equations with k+1 variables, the approach is by solving step by step from a chosen x₁.

FIG. 1 illustrates an example non-limiting schematic diagram 100 of a model of a neuron according to an aspect or embodiment of the subject disclosure.

As illustrated in FIG. 1, Hopfield neural networks are constructed with artificial neurons with n inputs and each input has a weight value. Output of each neuron is determined by the sum of all the weighted input. Let the current state of the i-th neuron denoted by S_(i,t), the next state S_(i,t+1), depends on the current states of other neurons and the synaptic weights as:

$\begin{matrix} {{S_{i,{t + 1}} = {f\left( {{\overset{n}{\sum\limits_{j = 1}}{\tau_{i,j}S_{j,t}}} + \vartheta_{i}} \right)}},{i = 1},2,{\ldots \mspace{14mu} n}} & {{Equation}\mspace{14mu} (1)} \end{matrix}$

where τ_(i,j) is the synaptic strength between neurons i and j, θ_(i) is the threshold value of the neuron i and ƒ(.) is any non-linear function. This equation is embodied in the diagram 100 shown in FIG. 1, where the artificial neurons at S_(1,t) (102), S_(2,t) (104), and S_(3,t) (106) are summed at 108 and then a function f is applied at 110, resulting in S_(i,t+1) at 112. Typically each neuron has two working states S_(i,t), firing state represented by S_(i,t)=1 and quiescent state represented by S_(i,t)=0. Hence, in HNN, ƒ(.) could take form of a signum function defined by

${f(x)} = \left\{ \begin{matrix} 1 & {{{if}\mspace{14mu} x}>=0} \\ 0 & {{{if}\mspace{14mu} x} < 0.} \end{matrix} \right.$

According to Hebb's learning rule, the synaptic weights τ_(ij) could be any real number, which is not friendly to its physical implementations. The Clipped Hopfield Neural Network (CHNN) clipped the synaptic weights into three values {+1, 0, −1} using Equation 2 shown below

$\begin{matrix} {\tau_{ij} = {{{\phi \left( \tau_{ij} \right)}\mspace{14mu} {and}\mspace{14mu} {\phi (x)}} = \left\{ \begin{matrix} {+ 1} & {{{if}\mspace{14mu} x} > 0} \\ 0 & {{{if}\mspace{14mu} x} = 0} \\ {- 1} & {{{if}\mspace{14mu} x} < 0} \end{matrix} \right.}} & {{Equation}\mspace{14mu} (2)} \end{matrix}$

and explored its non-linear dynamics and convergence properties in a design of a keystream generator. CHNN can also be constructed using linear feedback shift sequences with a non-linear filter function, which is irreducible in the field of GF(p) and has been theoretically proved to be NP-complete in nature. In this disclosure, CHNN is extended to be better applied in our proposed algorithm. For the extended CHNN, synaptic matrix T is generated as any unimodular besides idempotent matrix and the non-linear function ƒ(.) takes the form of

${f(x)} = \left\{ \begin{matrix} {x\mspace{14mu} {mod}\mspace{14mu} p} & {{{if}\mspace{14mu} x}>=0} \\ {p - {{x}\mspace{14mu} {mod}\mspace{14mu} p}} & {{{if}\mspace{14mu} x} < 0} \end{matrix} \right.$

where p is a large prime number, which means each neuron represents (└log₂p┘+1) bit of information, where └.┘ is the integer function.

When mapping from MVC to extended CHNN observing that S_(i,t+1) could be represented in matrix form, as t increases, it could be regarded as an enhanced multivariate scheme of using a large set of modular equations of low degree modulo a large number, compared with the two conventional schemes mentioned earlier. The solving of equations using both iterative and polynomial forms can be possible. Thus, the extended CHNN could be well mapped into multivariate problems. Rewriting Equation 1:

$\begin{matrix} {S_{1,{t + 1}} = {f\left( {{\overset{n}{\sum\limits_{j = 1}}{\tau_{1,j}S_{j,t}}} + \vartheta_{1}} \right)}} \\ {S_{2,{t + 1}} = {f\left( {{\overset{n}{\sum\limits_{j = 1}}{\tau_{2,j}S_{j,t}}} + \vartheta_{2}} \right)}} \\ \vdots \\ {S_{n,{t + 1}} = {f\left( {{\overset{n}{\sum\limits_{j = 1}}{\tau_{n,j}S_{j,t}}} + \vartheta_{n}} \right)}} \end{matrix}$

which could be further reformulated as

$\begin{matrix} {{S_{t + 1} = {{f\left( {{TS}_{t} + \vartheta} \right)}\mspace{14mu} {where}}}{{S_{t} = \begin{bmatrix} S_{1,t} \\ S_{2,t} \\ \vdots \\ S_{n,t} \end{bmatrix}},{\vartheta = \begin{bmatrix} \vartheta_{1} \\ \vartheta_{2} \\ \vdots \\ \vartheta_{n} \end{bmatrix}},{T = {\begin{bmatrix} \tau_{1,1} & \tau_{1,2} & \ldots & \tau_{1,n} \\ \tau_{2,1} & \tau_{2,2} & \ldots & \tau_{2,n} \\ \vdots & \vdots & \ddots & \vdots \\ \tau_{n,1} & \tau_{n,2} & \ldots & \tau_{n,n} \end{bmatrix}.}}}} & {{Equation}\mspace{14mu} (3)} \end{matrix}$

Synaptic matrix T can be an unimodular, which provides sufficient condition that the elements of its inverse T⁻¹ are all integers. This prerequisite secures the accuracy of the cryptosystem since the inverse matrix T⁻¹ will be iterated thousands of times in decryption stage on machines with limited precision. If the initial state of the network at t=0 is denoted as S₀ and let ƒ(.) function take the form of modulo operation, with the properties provided by the modulo arithmetic, such as

$\begin{matrix} {{f\left( {{{af}(b)} + c} \right)} = {\left\lbrack {{a\left( {b\mspace{14mu} {mod}\mspace{14mu} p} \right)} + c} \right\rbrack {mod}\mspace{14mu} p}} \\ {= {\left( {{ab} + c} \right){mod}\mspace{14mu} p}} \\ {= {f\left( {{ab} + c} \right)}} \end{matrix}$

the state after ρ times iterations can be derived as following:

$\begin{matrix} {{S_{1} = {f\left( {{TS}_{0} + \vartheta} \right)}}{S_{2} = {{f\left( {{TS}_{1} + \vartheta} \right)} = {{f\left( {{{Tf}\left( {{TS}_{0} + \vartheta} \right)} + \vartheta} \right)} = {f\left( {{T^{2}S_{0}} + {T\; \vartheta} + \vartheta} \right)}}}}{S_{3} = {{f\left( {{TS}_{2} + \vartheta} \right)} = {{f\left( {{{Tf}\left( {{T^{2}S_{0}} + {T\; \vartheta} + \vartheta} \right)} + \vartheta} \right)} = {f\left( {{T^{3}S_{0}} + {T^{2}\vartheta} + {T\; \vartheta} + \vartheta} \right)}}}}\vdots} & \; \\ {S_{\rho} = {{f\left( {{T^{\rho}S_{0}} + {\underset{j = 0}{\sum\limits^{\rho - 1}}{T^{j}\vartheta}}} \right)}.}} & {{Equation}\mspace{14mu} (4)} \end{matrix}$

Evidently, the neural network reaches the state, i.e. S_(p)=Y, where Y is the solution for the multivariate polynomials represented by T^(ρ)S₀+Σ_(j=0) ^(ρ−1)T^(j)θ with the input variable matrix

$X = {\begin{bmatrix} x_{1} \\ x_{2} \\ \vdots \\ x_{n} \end{bmatrix} = {S_{0} = {\begin{bmatrix} S_{1,0} \\ S_{2,0} \\ \vdots \\ \; \end{bmatrix}.}}}$

Equation (4) can be rewritten as multivariate polynomials in GF(p) as following

$\begin{matrix} {\begin{matrix} {Y = {f\left( {{T^{\rho}S_{0}} + {\sum\limits_{j = 0}^{\rho - 1}\; {T^{j}\vartheta}}} \right)}} \\ {= {f\left( {{T_{x}X} + {T_{\vartheta}\vartheta}} \right)}} \end{matrix}{where}T_{x} = {{T^{\rho}\mspace{14mu} {and}\mspace{14mu} T_{\vartheta}} = {\sum\limits_{j = 0}^{\rho - 1}{T^{j}.}}}} & {{Equation}\mspace{14mu} (5)} \end{matrix}$

From Equation (5), X can be obtained by:

X=ƒ(T _(x) ⁻¹(Y−ƒ(T _(θ)θ))).  Equation (6):

At this point, the mapping from the eCHNN to multivariate can be achieved.

In order to mitigate attacks due to the inverse properties of the Affine Matrix which can be found by either plaintext attacks or factorization attacks, random key pairs based on Diffie-Hellman-like key exchange can be generated. A method to obtain the shared threshold vector is described to enhance the security of the system

As discussed above, multivariate cryptography could be well mapped with the extended Clipped Hopfield Neural Network. However, without any supplementary steps, any one could easily break the system since if T and θ are set as public, to calculate inverse T⁻¹ involves no hardness. Even though the iteration time ρ could be kept as private and transformed from one party to the other through a secret channel, the cryptosystem could be broken in a worst-case time proportional to ρ and an average time of half that using brute-force attack.

To address the problems mentioned above, the subject application discloses that both parties to generate a matrix pair {T_(s),T_(s)′}, where E≡T_(s) ^(ρ)T′_(s) ^(ρ) mod p and E is a n×n unit array, instead of applying matrix T directly in the encryption and decryption processes indicated by (5) and (6). The method adopts the basic idea of Diffie-Hellman key exchange scheme and extends it into matrix field. The subject application first gives a brief overview of Diffie-Hellman key exchange scheme and then present the details of our proposed key scheme.

Diffie-Hellman key exchange algorithm provides the basis of a variety of key agreement protocols. The scheme offers a way to generate a shared key between two parties, say Alice and Bob, even without any prior communication. The protocol simply goes as follows. 1. Alice and Bob firstly agree on the use of a large prime number p and integer g, which is a primitive of mod p. 2. Alice picks a large integer a then calculates and sends Bob A=g^(a) mod p. 3. Bob picks a large integer b then calculates and sends Alice B=g^(b) mod p. 4. Alice calculates S_(A)=Ba mod p and Bob calculates S_(B)=A^(b) mod p where S_(A)=S_(B) for (g^(a))^(b) mod p=g^(ab) mod p=(g^(b))^(a) mod p.

It released cryptography from the need of a secure key distribution channel. Its security rests crucially on the difficulty of computing discrete logarithms in a finite field, namely Discrete Logarithms Problem (DLP). Diffie-Hellman key agreement algorithm could be easily extended to work with multi-parties in group communications. In disclosure herein, the DLP is introduced to a matrix field, which means given two n order matrices T, T^(o) and a large prime number p, find an integer l such that T^(l)≡T^(o) mod p. With the agreement of the use of T, T⁻¹ and p, the approach to get T_(s) and T′_(s) could be described as following steps:

1. Alice picks a large integer a and sends Bob

T _(A) =T ^(a) mod p  Equation (7):

T′ _(A)=(T ⁻¹)^(a) mod p  Equation (8):

2. Bob picks a large integer b and sends Alice

T _(B) =T ^(b) mod p  Equation (9):

T′ _(B)=(T ⁻¹)^(b) mod p  Equation (10):

3. Alice calculates

T _(s) =T _(B) ^(a) mod p  Equation (11):

T′ _(s)=(T′ _(B))^(a) mod p  Equation (12):

and Bob calculates

T _(s) =T _(A) ^(b) mod p  Equation (13):

T′ _(s)=(T′ _(A))^(b) mod p  Equation (14):

where T_(s) is used to encrypt while T′_(s) is used to decrypt, and vice versa.

Since a shared matrix pair {T_(s), T′_(s)} can be obtained using schemes described above, here the disclosure describes the way to generate the threshold vector using T_(s) as the base matrix. The schedule here exploits the properties of the multiplication of matrices. Alice and Bob firstly agree on the use of a mask vector Q=(q₁, q₂, . . . , q_(n)), which is randomly generated before any communication. To obtain the shared threshold vector, for Alice, the following steps are followed

1. randomly generates a set of vector V_(A)=(α₁, α₂, . . . , α_(u)) of random length u, where α_(i) is an integer for i=1, 2, . . . , u, as her secret key and calculates the sum:

$\begin{matrix} {H_{A} = {\sum\limits_{i = 1}^{u}\; {T_{s}^{\alpha_{i}}{mod}\; p}}} & {{Equation}\mspace{14mu} (15)} \end{matrix}$

2. If H_(A) is a singular matrix, Alice should go back to step 1) to re-generate the private key V_(A), otherwise calculate her public key using:

P _(A) =QH _(A) mod p  Equation (16):

For Bob, the following steps are followed:

1. randomly generates a set of vector V_(B)=(β₁, β₂, . . . , β_(v)) of random length v, where β_(j) is an integer for j=1, 2, . . . , v, as his secret key and calculates the sum

$\begin{matrix} {H_{B} = {\sum\limits_{j = 1}^{v}\; {T_{s}^{\beta_{j}}{mod}\; p}}} & {{Equation}\mspace{14mu} (17)} \end{matrix}$

2. If H_(B) is singular, Bob should go back to step 1) to re-generate the private key V_(B), otherwise calculate his public key using

P _(B) =QH _(B) mod p  Equation (18):

Alice and Bob exchange P_(A) and P_(B) and keep V_(A) and V_(B) secretly. In order to get the shared threshold vector, Alice will calculate

$\begin{matrix} \begin{matrix} {\vartheta_{A} = {P_{B}H_{A}{mod}\; p}} \\ {= {Q{\sum\limits_{j = 1}^{v}\; {T_{s}^{\beta_{j}}{\sum\limits_{i = 1}^{u}\; {T_{s}^{\alpha_{i}}{mod}\; p}}}}}} \\ {= {Q{\sum\limits_{j = 1}^{v}\; {\sum\limits_{i = 1}^{u}\; {T_{s}^{\beta_{j} + \alpha_{i}}{mod}\; p}}}}} \end{matrix} & {{Equation}\mspace{14mu} (19)} \end{matrix}$

and Bob will calculate

$\begin{matrix} \begin{matrix} {\vartheta_{B} = {P_{A}H_{B}{mod}\; p}} \\ {= {Q{\sum\limits_{i = 1}^{u}\; {T_{s}^{\alpha_{i}}{\sum\limits_{j = 1}^{v}\; {T_{s}^{\beta_{j}}{mod}\; p}}}}}} \\ {= {Q{\sum\limits_{i = 1}^{u}\; {\sum\limits_{j = 1}^{v}\; {T_{s}^{\alpha_{i} + \beta_{j}}{mod}\; p}}}}} \end{matrix} & {{Equation}\mspace{14mu} (20)} \end{matrix}$

Here: θ_(A)=θ_(B)=θ^(T). Thus, these steps lead to an agreement on the n×1 threshold vector d to be used in encryption and decryption between Alice and Bob.

With the key schedule stated in above, the shared matrix pair {T_(s),T′_(s)} and threshold vector are substituted in the neural cryptosystem, the encryption Equation (5) could be re-written as

$\begin{matrix} {C = {f\left( {{T_{s}^{\rho}M} + {\sum\limits_{j = 0}^{\rho - 1}\; {T_{s}^{j}\vartheta}}} \right)}} & {{Equation}\mspace{14mu} (21)} \end{matrix}$

where M coded as M=(m₁, m₂, . . . , m_(n))^(T) stands for the message to be sent from Alice to Bob, C is the cipher text. Alice then assembles message (C,ρ) and sends it to Bob. After extraction of C and ρ, Bob decrypts to get M, extracting

$\begin{matrix} {M = {f\left( {T_{s}^{\prime\rho}\left( {C - {f\left( {\sum\limits_{j = 0}^{\rho - 1}\; {T_{s}^{j}\vartheta}} \right)}} \right)} \right)}} & {{Equation}\mspace{14mu} (22)} \end{matrix}$

For the sake of simplicity but without loss of generality, small integers are used in examples herein instead of large ones. For n=4 and p=23 in GF(23) space, mask vector Q=(22,5,12,3), unimodular T and T⁻¹ are given as

$T = \begin{bmatrix} 0 & {- 1} & {- 4} & {- 4} \\ 1 & 4 & {- 6} & 0 \\ {- 2} & {- 7} & {- 2} & {- 9} \\ 1 & 3 & {- 3} & 1 \end{bmatrix}$ and ${T^{- 1} = \begin{bmatrix} 4 & {- 1} & {- 2} & {- 2} \\ {- 13} & {- 4} & 8 & 20 \\ {- 8} & {- 3} & 5 & 13 \\ 11 & 4 & {- 7} & 18 \end{bmatrix}},$

Suppose Alice selects a=55 and T_(A) and T′_(A) could be calculated by using (7) and (8). Similarly, Bob chooses b=69 and computes T_(B) and T_(B)′ using (9) and (10). Then Alice and Bob could synchronize a shared matrix pair {T_(s),T′_(s)} as the base matrix used to generate the threshold vector, where

$T_{A} \equiv T^{55} \equiv {\begin{bmatrix} 10 & 3 & 18 & 6 \\ 0 & 22 & 20 & 3 \\ 8 & 7 & 12 & 21 \\ 16 & 14 & 11 & 10 \end{bmatrix}{mod}\; 23}$ $T_{A}^{\prime} \equiv T^{- 155} \equiv {\begin{bmatrix} 17 & 21 & 13 & 16 \\ 22 & 22 & 7 & 0 \\ 20 & 0 & 19 & 1 \\ 12 & 0 & 6 & 1 \end{bmatrix}{mod}\; 23}$ $T_{B} = {T^{69} \equiv {\begin{bmatrix} 5 & 15 & 20 & 2 \\ 22 & 22 & 3 & 9 \\ 19 & 9 & 13 & 1 \\ 10 & 11 & 8 & 6 \end{bmatrix}{mod}\; 23}}$ $T_{B}^{\prime} \equiv T^{- 169} \equiv {\begin{bmatrix} 13 & 21 & 12 & 12 \\ 0 & 16 & 13 & 16 \\ 5 & 3 & 16 & 18 \\ 10 & 16 & 0 & 15 \end{bmatrix}{mod}\; 23}$ $\begin{matrix} {T_{s} \equiv {\begin{bmatrix} 5 & 15 & 20 & 2 \\ 22 & 22 & 3 & 9 \\ 19 & 9 & 13 & 1 \\ 10 & 11 & 8 & 6 \end{bmatrix}^{55}{mod}\; 23}} \\ {\equiv {\begin{bmatrix} 10 & 3 & 18 & 6 \\ 0 & 22 & 20 & 3 \\ 8 & 7 & 12 & 21 \\ 16 & 14 & 11 & 10 \end{bmatrix}^{69}{mod}\; 23}} \\ {\equiv {\begin{bmatrix} 8 & 6 & 13 & 11 \\ 21 & 14 & 6 & 7 \\ 10 & 8 & 9 & 13 \\ 10 & 22 & 4 & 14 \end{bmatrix}{mod}\; 23}} \end{matrix}$ $\begin{matrix} {T_{s}^{\prime} \equiv {\begin{bmatrix} 13 & 21 & 12 & 12 \\ 0 & 16 & 13 & 16 \\ 5 & 3 & 16 & 18 \\ 10 & 16 & 0 & 15 \end{bmatrix}^{- 55}{mod}\; 23}} \\ {\equiv {\begin{bmatrix} 17 & 21 & 13 & 16 \\ 22 & 22 & 7 & 0 \\ 20 & 0 & 19 & 1 \\ 12 & 0 & 6 & 1 \end{bmatrix}^{69}{mod}\; 23}} \\ {\equiv {\begin{bmatrix} 21 & 17 & 12 & 0 \\ 6 & 4 & 15 & 4 \\ 15 & 4 & 4 & 17 \\ 14 & 10 & 16 & 7 \end{bmatrix}{mod}\; 23}} \end{matrix}$

Now that the base matrix pair {T_(s), T′_(s)} have been generated, Alice and Bob select V_(A)=(11,2,13,4) and V_(B)=(5,146,7,8,99) as their secret key respectively and the public keys could be obtained by substituting these parameters into Equations (16) and (18) resulting in

$\begin{matrix} {P_{A} \equiv {f\left( {Q\left( {T_{s}^{11} + T_{s}^{2} + T_{s}^{13} + T_{s}^{4}} \right)} \right)}} \\ {\equiv {{\begin{bmatrix} 22 \\ 5 \\ 12 \\ 3 \end{bmatrix}^{T}\begin{bmatrix} 5 & 1 & 13 & 1 \\ 4 & 7 & 6 & 10 \\ 18 & 22 & 19 & 13 \\ 10 & 10 & 22 & 7 \end{bmatrix}}{mod}\; 23}} \\ {\equiv {\begin{bmatrix} 8 & 6 & 12 & 19 \end{bmatrix}{mod}\; 23}} \end{matrix}$ $\begin{matrix} {P_{B} \equiv {f\left( {Q\left( {T_{s}^{5} + T_{s}^{146} + T_{s}^{7} + T_{s}^{8} + T_{s}^{99}} \right)} \right)}} \\ {\equiv {{\begin{bmatrix} 22 \\ 5 \\ 12 \\ 3 \end{bmatrix}^{T}\begin{bmatrix} 11 & 17 & 5 & 8 \\ 16 & 7 & 16 & 11 \\ 11 & 11 & 17 & 7 \\ 10 & 16 & 1 & 22 \end{bmatrix}}{mod}\; 23}} \\ {\equiv {\begin{bmatrix} 1 & 4 & 6 & 13 \end{bmatrix}{mod}\; 23}} \end{matrix}$

Then the shared vector could be calculated as using Equations (19) and (20) by Alice and Bob respectively as

$\begin{matrix} {\vartheta_{A} \equiv {{\begin{bmatrix} 1 \\ 4 \\ 6 \\ 13 \end{bmatrix}^{T}\begin{bmatrix} 5 & 1 & 13 & 1 \\ 4 & 7 & 6 & 10 \\ 18 & 22 & 19 & 13 \\ 10 & 10 & 22 & 7 \end{bmatrix}}{mod}\; 23}} \\ {\equiv \left\lbrack \begin{matrix} 0 & 16 & 14 & {\left. 11 \right\rbrack {mod}\; 23} \end{matrix} \right.} \end{matrix}$ $\begin{matrix} {\vartheta_{B} = {{\begin{bmatrix} 8 \\ 6 \\ 12 \\ 19 \end{bmatrix}^{T}\begin{bmatrix} 11 & 17 & 5 & 8 \\ 16 & 7 & 16 & 11 \\ 11 & 11 & 17 & 7 \\ 10 & 16 & 1 & 22 \end{bmatrix}}{mod}\; 23}} \\ {\equiv \left\lbrack \begin{matrix} 0 & 16 & 14 & {\left. 11 \right\rbrack {mod}\; 23} \end{matrix} \right.} \end{matrix}$

Let M=(11,16,3,7)^(T) and ρ=600, Alice calculates C=(4,11,19,14)^(T) using (21) and sends Bob (4,11,19,14,600). Bob then decrypts using (22) and gets M=(11,16,3,7)^(T)

The above process for encryption and decryption is shown in the flowchart in FIG. 2, which illustrates an example non-limiting schematic diagram 200 of a cryptosystem flow according to an aspect or embodiment of the subject disclosure.

As shown in FIG. 2, several stages are involved in the communication which could be classified into three stages, the initial stage 202, the synchronization stage 204 and 206 and the encryption/decryption stage 208. In the initial stage 202, system parameters including n, p, T and Q are agreed and private keys {a,V_(A)} and {b,V_(B)} are randomly generated by Alice and Bob respectively. In the synchronization stages, the base matrix pair {T_(s),T_(s)′} (204) and the threshold vector θ (206) are obtained using schemes described above. Hence, the two sides Alice and Bob could use them to communicate, illustrated as the encryption/decryption stage 208 in FIG. 2. Initialization and synchronization can be done only once before the first communication of two parties. In order to obtain higher security, the iteration time ρ can be kept as a variable for different sessions.

From the security standpoint, a reliable cryptosystem should be designed with high sensitivity to the key and the plaintext. In order to obtain more visualized details, two plaintexts represented by (x,y) can be traversed and keys with slightly difference in a CHNN-MVC of two nodes, which are numbered as neuron 1 for x and neuron 2 for y. The output results with different values of ρ then could be traversed and described as points in a X-Y coordinate. As depicted in FIG. 3 and FIG. 4, the results changed dramatically with slight difference added into plaintext by transforming (3, 11) to (2, 11). Small changes of the key vector by transforming V_(A)=(11,2,13,4) to V_(A)=(11,2,13,4,1) also leads to tremendous differences in the output, as illustrated in FIG. 3 and FIG. 5. Similarly, a small change of one party's secret iteration number by transforming b=11 to b=13 gives entirely different results as illustrated in FIG. 3 and FIG. 6. It shows high level of sensitivity to plaintext, key and iteration number of our scheme

FIG. 3 depicts data traversing 1 of Plaintext (3,11) with Q=(12,17), a=17, b=11, V_(A)=(11,2,13,4), V_(B)=(5,1,7,8,19), ρ from 10 to 19; FIG. 4 depicts data traversing of Paintext (2,11) with Q=(12,17), a=17, b=11, V_(A)=(11,2,13,4), V_(B)=(5,1,7,8,19), ρ from 10 to 19; FIG. 5 depicts data traversing 2 of Plaintext (3,11) with Q=(12,17), a=17, b=11, V_(A)=(11,2,13,4,1), V_(B)=(5,1,7,8,19), ρ from 10 to 19; while FIG. 6 depicts data traversing 3 of Plaintext (3,11) with Q=(12,17), a=17, b=13, V_(A)=(11,2,13,4), V_(B)=(5,1,7,8,19), p from 10 to 19.

Compared with traditional algorithms, vectors and matrixes instead of single data are used as keys in our scheme, which means the output comes as a combination of the effect of multiple data by means of matrix multiplication and due to the system's high sensitivity to the key, to break the system, one need to hit all the elements of the matrix correctly at the same time and namely the cryptography is multi-dimensional. Accordingly, potential attacks on it are analyzed to show its strong security. The following depicts exemplary proposed attacks on the disclosed eCHNN encryption scheme.

One possible way to attack the proposed DH-like matrix exchange algorithm is by applying matrix decomposition. As introduced in Section 3.1, T is set as public, given T_(A) (or T_(B)), the analyser may try to factorize T to obtain its power expression to get the exponent a (or b). The most likely factorizing method is the eigendecomposition, which will decompose matrix T into the product of PDP⁻¹, where D is a diagonal matrix formed by the distinct eigenvalues of T and P is the matrix generated using the corresponding eigenvectors of T as its columns. For the sake of simplicity, consider T as a 2×2 matrix and suppose

${T_{A} = \begin{bmatrix} t_{1} & t_{2} \\ t_{3} & t_{4} \end{bmatrix}},{D = \begin{bmatrix} \lambda_{1} & 0 \\ 0 & \lambda_{2} \end{bmatrix}},{P = \begin{bmatrix} \eta_{1} & \eta_{2} \\ \eta_{3} & \eta_{4} \end{bmatrix}},{P^{- 1} = \begin{bmatrix} \eta_{1}^{\prime} & \eta_{2}^{\prime} \\ \eta_{3}^{\prime} & \eta_{4}^{\prime} \end{bmatrix}}$

where λ₁ and λ₂ are the two distinct eigenvalues of matrix T. Apparently, there's

$\begin{matrix} \left\{ \begin{matrix} {{{{\eta_{1}\eta_{1}^{\prime}} + {\eta_{2}\eta_{3}^{\prime}}} = 1},} \\ {{{{\eta_{1}\eta_{2}^{\prime}} + {\eta_{2}\eta_{4}^{\prime}}} = 0},} \\ {{{{\eta_{3}\eta_{1}^{\prime}} + {\eta_{4}\eta_{3}^{\prime}}} = 0},} \\ {{{\eta_{3}\eta_{2}^{\prime}} + {\eta_{4}\eta_{4}^{\prime}}} = 1.} \end{matrix} \right. & {{Equation}\mspace{14mu} (23)} \end{matrix}$

Since T=PDP⁻¹ and as defined in Section 3.1 T_(A)≡T^(a) mod p, the following pertains

$\begin{matrix} \begin{matrix} {T^{a} = \left( {PDP}^{- 1} \right)^{a}} \\ {= {\left( {PDP}^{- 1} \right)\left( {PDP}^{- 1} \right)\mspace{14mu} \ldots \mspace{14mu} \left( {PDP}^{- 1} \right)}} \\ {= {{PD}^{a}{PD}^{- 1}}} \end{matrix} & {{Equation}\mspace{14mu} (24)} \end{matrix}$

which could be further developed as

$T_{A} = {{{\begin{bmatrix} \eta_{1} & \eta_{2} \\ \eta_{3} & \eta_{4} \end{bmatrix}\begin{bmatrix} \lambda_{1} & 0 \\ 0 & \lambda_{2} \end{bmatrix}}^{a}\begin{bmatrix} \eta_{1}^{\prime} & \eta_{2}^{\prime} \\ \eta_{3}^{\prime} & \eta_{4}^{\prime} \end{bmatrix}}{mod}\; p}$

With the expansion of Equation (24) and substitutions of Equation (23), to break the DH-like matrix exchange algorithm is equivalent to solve a from the following equations:

$\quad\left\{ \begin{matrix} {{t_{1} \equiv {{\eta_{1}\eta_{1}^{\prime}\lambda_{1}^{a}} + {\left( {1 - {\eta_{1}\eta_{1}^{\prime}}} \right)\lambda_{2}^{a}{{mod}p}}}},} \\ {{t_{2} \equiv {{\eta_{1}\eta_{2}^{\prime}\lambda_{1}^{a}} - {\eta_{1}\eta_{2}^{\prime}\lambda_{2}^{a}{mod}\; p}}},} \\ {{t_{3} \equiv {{\eta_{3}\eta_{1}^{\prime}\lambda_{1}^{a}} - {\eta_{3}\eta_{1}^{\prime}\lambda_{2}^{a}{mod}\; p}}},} \\ {t_{4} \equiv {{\eta_{3}\eta_{2}^{\prime}\lambda_{1}^{a}} + {\left( {1 - {\eta_{3}\eta_{2}^{\prime}}} \right)\lambda_{2}^{a}{mod}\; {p.}}}} \end{matrix} \right.$

This is much harder than solving general discrete logarithms even it is worked with quantum computers because the exponent a has to satisfy multiple discrete logarithm equations with multiple bases at the same time. Worse still, for the reason of the limited machine precision and with a large integer a, truncation error will lead the solution into uncontrollable status since the distinct eigenvalues are more likely to be decimals than integers. Consequently, the proposed DH-like matrix exchange algorithm disclosed herein is secure against attacks of matrix decompositions.

Another possible way to attack the proposed DH-like matrix exchange algorithm is by a one way function attack. The one way function in Section 3.2 is defined as given two row vectors of length n, Q and V, find a non-singular matrix

such that

≡V mod p. Explicitly H_(A) is a solution of

≡P_(A) mod p and H_(B) is a solution of

≡P_(B) mod p. To derive secret keys H_(A) and H_(B) from public keys P_(A) and P_(B) is equivalent to determine a specific matrix which satisfies the equation. Suppose

V = (v₁, v₂, …  , v_(n)) and $T^{\clubsuit} = \begin{bmatrix} \gamma_{11} & \gamma_{21} & \ldots & \gamma_{n\; 1} \\ \gamma_{12} & \gamma_{22} & \ldots & \gamma_{n\; 2} \\ \vdots & \vdots & \vdots & \vdots \\ \gamma_{1n} & \gamma_{2n} & \ldots & \gamma_{nm} \end{bmatrix}$

where v_(i) and γ_(ij) are all primitives of GF(p), for i, j=1, 2, . . . , n, the problem could be turned to find solutions of the equation set in terms of modulo p, as illustrated in the following equation

${\begin{bmatrix} q_{1} \\ q_{2} \\ \vdots \\ q_{n} \end{bmatrix}^{T}\begin{bmatrix} \gamma_{11} & \ldots & \gamma_{n\; 1} \\ \gamma_{12} & \ldots & \gamma_{n\; 2} \\ \vdots & \vdots & \vdots \\ \gamma_{1n} & \ldots & \gamma_{nm} \end{bmatrix}} = {f\left( \begin{bmatrix} v_{1} \\ v_{2} \\ \vdots \\ v_{n} \end{bmatrix}^{T} \right)}$

which could be rewritten as

$\begin{matrix} \left\{ \begin{matrix} {{{\sum\limits_{i = 1}^{n}\; {q_{i}\gamma_{1i}}} \equiv {v_{1}{mod}\; p}},} \\ {{{\sum\limits_{i = 1}^{n}\; {q_{i}\gamma_{2i}}} \equiv {v_{2}{mod}\; p}},} \\ \vdots \\ {{\sum\limits_{i = 1}^{n}\; {q_{i}\gamma_{ni}}} \equiv {v_{n}{mod}\; {p.}}} \end{matrix} \right. & {{Equation}\mspace{14mu} (25)} \end{matrix}$

The Key space of Equation (25) is approximately infinite as p is chosen as an RSA integer. Consequently, the schemed disclosed herein could be secure against such one way function attacks.

Since CHNN is based on permuting their indices and in fact {circumflex over (T)} is obtained by conjugating T with the permutation P, i.e., the first the rows of T are permuted according to P and then the elements of each row are permuted according to P. Such an operation will not change the static structure of the network. The output of the permuted network can be identical to the result obtained by permuting the input to the regular network according to P and then permuting the network output according to the inverse of P, which is a faster cryptoanalysis procedure than permuting the network itself. This function of the network is just a nonlinear mapping and thus cipher only attack can break the system. This cryptanalysis approach is also valid for static Affine Matrices used in MVC systems.

With the introduction of the DH like key protocol into the MVC based CHNN cryptosystem, the static structure becoming dynamic and the mapping now becomes non-linear by selecting a non-singular key generation matrices H_(A) and H_(R). Thus, the Cipher Only Attack can be mitigated.

Affine matrices used in MVC systems can be singular, and by knowing the public key matrix and substituting a known plaintext into the key equations, a new matrix M can be obtained which can then be used to find the uniquely inversion of the matrix M and thus the private key matrix. By introducing a non-singular key generation matrices H_(A) and H_(B), the key pair matrices are no longer singular and thus the mapping becomes non-linear and thus, the known Plaintext Attack can be mitigated.

Since the proposed CHNN cryptosystem mapping directly into a Multivariate Cryptographic System, the NP hardness properties of the system will be preserved. For a n-neuron CHNN, the number of attractors selected as coded plaintext is P and the number of coding matrices will be P!, and for any given coding matrix. The key space will be n!. No simple known plaintext attack and key matrix factorization or decomposition can applied and an exhaustive search will need over n! number of search for unveiling the key pairs. In addition the scheme used to generate the threshold vector extremely extends the key space as illustrated by the following discussion. Due to the nature of mod operation, repetitive feature exits in T^(ρ) mod p. Let the repetitive period denoted as Δ, the characteristic could be described as

T ^(ρ) mod p=T ^(ρ+Δ)mod p

which equivalents to

T ^(Δ) mod p=E mod p  Equation (26):

Evidently, space of T_(s), indicated as Θ(T,Δ,p) crucially rests with value of Δ, since

T _(s) mod p=T ^(ab mod Δ) mod p.  Equation (27):

Hence, there will be

Θ=T mod p,T ² mod p, . . . ,T ^(Δ) mod p.

In order to give one possible way to derive A, the characteristic equation t(s) of the n×n unimodular matrix T can be considered. For any polynomial P(s), there is

P(s)=q(s)t(s)+r(s)  Equation (28):

where q(s) could be found by long division and the degree of the remainder polynomial r(s) is not larger than n−1. With the eigenvalues of matrix T given as λ₁, λ₂, . . . λ_(n), definitely t(λ_(i))=0, for i=1, 2, . . . , n. According to the Cayley-Hamilton theorem [28], an n×n matrix satisfies its characteristic equation, i.e. t(T)=0. In consequence, the order of a polynomial in T could be reduced using

P(T)=q(T)t(T)+r(T)=r(T)

Let P(T)=T^(Δ), the following equation can be obtained from above

$\begin{matrix} {T^{\Delta} = {{r(T)} = {{r_{0}E} + {\sum\limits_{i = 1}^{n - 1}\; {r_{i}{T^{i}.}}}}}} & {{Equation}\mspace{14mu} (29)} \end{matrix}$

Equation (26) could be converted into n² equations

$\begin{matrix} \left\{ {\begin{matrix} {{{\sum\limits_{i = 1}^{n - 1}\; {r_{i}\tau_{{\alpha\beta},{\alpha \neq \beta}}^{(i)}}} = {k_{\alpha\beta}p}},} \\ {{{\sum\limits_{i = 1}^{n - 1}\; {r_{i}\tau_{\alpha\alpha}^{(i)}}} + r_{0}} = {{k_{\alpha\alpha}p} + 1}} \end{matrix}.} \right. & {{Equation}\mspace{14mu} (30)} \end{matrix}$

where τ^((i)) _(αβ) denotes the (α,β) element of matrix T^(i) mod p, k_(αβ) is any integer for α,β=1, 2, . . . , n and r_(i) for i=0, 1, . . . , n−1 could be obtained by solving the n linear equations in n unknowns

$\begin{matrix} {\lambda_{j}^{\Delta} = {r_{0} + {\sum\limits_{i = 1}^{n - 1}\; {r_{i}\lambda_{j}^{i}}}}} & {{Equation}\mspace{14mu} (31)} \end{matrix}$

for j=1, 2, . . . , n. Δ could be found by solving (30) and (31) simultaneously with traversing all possible values of k_(Δε).

For simplicity if n=2 the problem turns to

$\quad\left\{ {\begin{matrix} {{{{r_{1}\tau_{11}} + r_{0}} = {{k_{11}p} + 1}},} \\ {{{r_{1}\tau_{12}} = {k_{12}p}},} \\ {{{r_{1}\tau_{21}} = {k_{21}p}},} \\ {{{r_{1}\tau_{22}} + r_{0}} = {{k_{22}p} + 1.}} \end{matrix}{where}\left\{ \begin{matrix} {{r_{0} = \frac{{\lambda_{1}\lambda_{2}^{\Delta}} - {\lambda_{2}\lambda_{1}^{\Delta}}}{\lambda_{1} - \lambda_{2}}},} \\ {r_{1} = {\frac{\lambda_{1}^{\Delta} - \lambda_{2}^{\Delta}}{\lambda_{1} - \lambda_{2}}.}} \end{matrix} \right.} \right.$

Therefore, λ₁ ^(Δ) and λ₂ ^(Δ) can be obtained as the following polynomials

$\quad\left\{ \begin{matrix} {{\lambda_{1}^{\Delta} = {{k_{22}p} + 1 + {\frac{k_{12}}{\tau_{12}}\left( {\lambda_{1} - \tau_{22}} \right)p}}},} \\ {{\lambda_{1}^{\Delta} = {{k_{22}p} + 1 + {\frac{k_{21}}{\tau_{21}}\left( {\lambda_{1} - \tau_{22}} \right)p}}},} \\ {{\lambda_{2}^{\Delta} = {{k_{11}p} + 1 + {\frac{k_{12}}{\tau_{12}}\left( {\lambda_{2} - \tau_{11}} \right)p}}},} \\ {\lambda_{2}^{\Delta} = {{k_{11}p} + 1 + {\frac{k_{21}}{\tau_{21}}\left( {\lambda_{2} - \tau_{11}} \right){p.}}}} \end{matrix} \right.$

Suppose k₁₂=τ₁₂k′ and k₂₁=τ₂₁k′, Δ could be solved as

$\begin{matrix} \left\{ \begin{matrix} {{\Delta = {{\log_{\lambda_{1}}k_{22}p} + 1 + {{k^{\prime}\left( {\lambda_{1} - \tau_{22}} \right)}p}}},} \\ {\Delta = {{\log_{\lambda_{2}}k_{11}p} + 1 + {{k^{\prime}\left( {\lambda_{2} - \tau_{11}} \right)}{p.}}}} \end{matrix} \right. & {{Equation}\mspace{14mu} (32)} \end{matrix}$

For the method of exhaustion, k₂₂, k′ and k₁₁ would be traversed in the integer field simultaneously to find all the possible solutions of each equation. Specifically, for p=7 and T is given as

$T = \begin{bmatrix} 5 & {- 4} \\ {- 6} & 5 \end{bmatrix}$

the eigenvalues could be calculated as

λ₁=5+√{square root over (6)}, λ₂=5−√{square root over (6)}.

When k₁₁=k₂₂=6585600 and k′=2688560, (32) has solution Δ=8. The computation of Δ becomes extremely complex, time and memory consuming when n gets larger since more k_(αβ) will be traversed in one equation. In addition, due to the issue of machine precision, the feasibility to calculate Δ applying Cayley Hamilton theorem is likely to be minimal. The main purpose of the derivation above is just show one way to estimate the space of T_(s).

Let the repetitive period of the shared matrix T_(s) represented by Δ′ and its relationship with Δ could be derived as following. Since there's T_(s) ^(ρ+A) ^(′) mod p=T_(s) ^(ρ) mod p, let ρ′=ab mod p, with Equation (27), it can be rewritten as T^(ρ) ^(′) ^((ρ+Δ) ^(′) ⁾ mod p=T^(ρ) ^(′) ^(ρ) mod p.

Clearly, then ρ′A′=0 mod Δ, which could be further solved as

${\Delta^{\prime} = {\frac{k}{\rho^{\prime}}\Delta}},$

where k is the smallest positive integer that ensures A′ an integer. Therefore, the repetitive period of T_(s) satisfies

$\Delta^{\prime} = {\frac{\Delta}{\gcd \left( {\Delta,\rho^{\prime}} \right)}.}$

where gcd(Δ,ρ′) denotes the greatest common divisor of Δ and ρ′.

At this point, it can be seen that there exists the probability of reduction of space of T_(s) ^(ρ) mod p compared with Δ, when gcd(Δ,ρ′)≠1, which is undesirable. However, this problem can be easily mitigated simply by changing the modulus p used in Section 3.2 slightly into p′. Some experimental results of Δ and Δ′ of different neuron networks are given in Table 0, which shows high efficiency of this measure and indicates A and A′ could be much larger than n². With the upper limit of μ and v restricted as ε, even if T_(s) has been successfully analyzed, the space of the key matrix H_(A) (or H_(B)) represented by Ω could be calculated as the sum of all possible combinations of the Δ values with repetition [5] as following:

$\begin{matrix} {\Omega = {\sum\limits_{i = 1}^{ɛ}\; \begin{pmatrix} {\Delta^{\prime} + i - 1} \\ i \end{pmatrix}}} & {{Equation}\mspace{14mu} (33)} \end{matrix}$

Next, if ε is set as n, there is

$\Omega \begin{pmatrix} {\Delta^{\prime} + ɛ - 1} \\ ɛ \end{pmatrix}\begin{pmatrix} {n^{2} + n - 1} \\ n \end{pmatrix}n^{n}{n!}$

A proof of this property is given in Appendix A. Considering that the maximum amount of matrices of order n defined in the finite field GF(p) is p^(n) ² , the brute force searching space of H_(A) (or H_(B)) will be min (Ω,p^(n) ² ) even if T_(s) is broken, using scheme described in Section 3.2. If a dedicated computer system that can perform a search of 10⁶ groups of random permutations of keys in one second, the time required to search exhaustively the entire private key space and to identify private key is dependent on the size of n; for n=32 more than 10³⁵ MIPS years would be required for a successful search, which is well above the acceptable security level of current states, i.e., 10¹² MIPS years.

FIG. 7 is an example non-limiting process flow diagram of a method 700 that encrypts communications based on a cryptosystem method, according to an aspect or embodiment of the subject disclosure. For simplicity of explanation, the methods (or procedures) are depicted and described as a series of acts. It is noted that the various embodiments are not limited by the acts illustrated and/or by the order of acts. For example, acts can occur in various orders and/or concurrently, and with other acts not presented or described herein. In another aspect, the various acts can be performed by systems and/or components of embodiments described herein.

Method 700 can begin at 702, where the method includes initializing a system parameter. At step 704, the method can include randomly generating a private key based on a Diffie-Hellman key exchange with a sending device.

At 706, the method can include generating a base matrix pair as a function of the private keys, wherein the base matrix pair is synchronized with the sending device. While at 708, the method can include determining a threshold vector using the system parameter and the private key.

At 710, the method can include decrypting a received message based on the threshold vector and the base matrix pair.

Turning now to FIG. 8, illustrated is an example non-limiting process flow diagram of a cryptosystem method 800 according to an aspect or embodiment of the subject disclosure. Method 800 can start at 802 where the method comprises determining, by a system comprising a processor, a set of system parameters. At 804, the method can include generating a random private key based on a Diffie-Hellman key exchange program with a device associated with a message recipient. At 806 the method can include generating a base matrix pair as a function of the private key that is synchronized with another base matrix pair of the message recipient. At 808, the method can include synchronizing a threshold vector with another threshold vector of the message recipient using a system parameter of the set of system parameters and the private key while at 810 the method can include encrypting a communication using the threshold vector and the synchronized base matrix pair.

Referring now to FIG. 9, there is illustrated a schematic block diagram of a computing environment 900 in accordance with this specification. The system 900 includes one or more client(s) 902, (e.g., computers, smart phones, tablets, cameras, PDA's). The client(s) 902 can be hardware and/or software (e.g., threads, processes, computing devices). The client(s) 902 can house cookie(s) and/or associated contextual information by employing the specification, for example.

The system 900 also includes one or more server(s) 904. The server(s) 904 can also be hardware or hardware in combination with software (e.g., threads, processes, computing devices). The servers 904 can house threads to perform transformations by employing aspects of this disclosure, for example. One possible communication between a client 902 and a server 904 can be in the form of a data packet adapted to be transmitted between two or more computer processes wherein data packets may include coded items. The data packet can include a cookie and/or associated contextual information, for example. The system 900 includes a communication framework 906 (e.g., a global communication network such as the Internet) that can be employed to facilitate communications between the client(s) 902 and the server(s) 904.

Communications can be facilitated via a wired (including optical fiber) and/or wireless technology. In an aspect, communications between client(s) 902 and network devices (e.g., server(s) 904) are through wireless channels. In another aspect, communication links between network devices (e.g., servers(s) 904) can be via wireless and/or wired channels. It is noted that wireless connections between client(s) 902 and network devices (e.g., server(s) 904) are described herein, however client(s) 902 may have other capabilities (e.g., wired communications capabilities). The client(s) 902 are operatively connected to one or more client data store(s) 908 that can be employed to store information local to the client(s) 902 (e.g., cookie(s) and/or associated contextual information). Similarly, the server(s) 904 are operatively connected to one or more server data store(s) 910 that can be employed to store information local to the servers 904.

In one implementation, a server 904 can transfer an encoded file, (e.g., network selection policy, network condition information, etc.), to client 902. Client 902 can store the file, decode the file, or transmit the file to another client 902. It is noted, that a server 904 can also transfer uncompressed file to a client 902 and client 902 can compress the file in accordance with the disclosed subject matter. Likewise, server 904 can encode information and transmit the information via communication framework 906 to one or more clients 902.

Referring now to FIG. 10, there is illustrated a block diagram of a computer operable to execute the disclosed communication architecture. In order to provide additional context for various aspects of the subject specification, FIG. 10 and the following discussion are intended to provide a brief, general description of a suitable computing environment 1000 in which the various aspects of the specification can be implemented. While the specification has been described above in the general context of computer-executable instructions that can run on one or more computers, it is noted that the specification also can be implemented in combination with other program modules and/or as a combination of hardware and software.

Generally, program modules include routines, programs, components, data structures, etc., that perform particular tasks or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputers, mainframe computers, as well as personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, and the like, each of which can be operatively coupled to one or more associated devices.

The illustrated aspects of the specification can also be practiced in distributed computing environments, including cloud-computing environments, where certain tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

Computing devices can include a variety of media, which can include computer-readable storage media and/or communications media, which two terms are used herein differently from one another as follows. Computer-readable storage media can be any available storage media that can be accessed by the computer and includes both volatile and nonvolatile media, removable and non-removable media. By way of example, and not limitation, computer-readable storage media can be implemented in connection with any method or technology for storage of information such as computer-readable instructions, program modules, structured data, or unstructured data. Computer-readable storage media can include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or other tangible and/or non-transitory media which can be used to store desired information. Computer-readable storage media can be accessed by one or more local or remote computing devices, e.g., via access requests, queries or other data retrieval protocols, for a variety of operations with respect to the information stored by the medium.

Communications media typically include (and/or facilitate the transmission of) computer-readable instructions, data structures, program modules or other structured or unstructured data in a data signal such as a modulated data signal, e.g., a carrier wave or other transport mechanism, and includes any information delivery or transport media. The term “modulated data signal” or signals refers to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in one or more signals. By way of example, and not limitation, communications media include wired media, such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media.

With reference again to FIG. 10, the example environment 1000 for implementing various aspects of the specification includes a computer 1002, the computer 1002 including a processing unit 1004, a system memory 1006 and a system bus 1008. The system bus 1008 couples system components including, but not limited to, the system memory 1006 to the processing unit 1004. The processing unit 1004 can be any of various commercially available processors. Dual microprocessors and other multi-processor architectures can also be employed as the processing unit 1004.

The system bus 1008 can be any of several types of bus structure that can further interconnect to a memory bus (with or without a memory controller), a peripheral bus, and a local bus using any of a variety of commercially available bus architectures. The system memory 1006 includes read-only memory (ROM) 1010 and random access memory (RAM) 1012. A basic input/output system is stored in a non-volatile memory 1010 such as ROM, erasable programmable read only memory, electrically erasable programmable read only memory, which basic input/output system contains the basic routines that help to transfer information between elements within the computer 1002, such as during startup. The RAM 1012 can also include a high-speed RAM such as static RAM for caching data.

The computer 1002 further includes an internal hard disk drive 1014 (e.g., EIDE, SATA), which internal hard disk drive 1014 can also be configured for external use in a suitable chassis (not shown), a magnetic floppy disk drive 1016, (e.g., to read from or write to a removable diskette 1018) and an optical disk drive 1020, (e.g., reading a CD-ROM disk 1022 or, to read from or write to other high capacity optical media such as the DVD). The hard disk drive 1014, magnetic disk drive 1016 and optical disk drive 1020 can be connected to the system bus 1008 by a hard disk drive interface 1024, a magnetic disk drive interface 1026 and an optical drive interface 1028, respectively. The interface 1024 for external drive implementations includes at least one or both of Universal Serial Bus (USB) and IEEE 1394 interface technologies. Other external drive connection technologies are within contemplation of the subject specification.

The drives and their associated computer-readable storage media provide nonvolatile storage of data, data structures, computer-executable instructions, and so forth. For the computer 1002, the drives and storage media accommodate the storage of any data in a suitable digital format. Although the description of computer-readable storage media above refers to a HDD, a removable magnetic diskette, and a removable optical media such as a CD or DVD, it should be noted by those skilled in the art that other types of storage media which are readable by a computer, such as zip drives, magnetic cassettes, flash memory cards, cartridges, and the like, can also be used in the example operating environment, and further, that any such storage media can contain computer-executable instructions for performing the methods of the specification.

A number of program modules can be stored in the drives and RAM 1012, including an operating system 1030, one or more application programs 1032, other program modules 1034 and program data 1036. All or portions of the operating system, applications, modules, and/or data can also be cached in the RAM 1012. It is noted that the specification can be implemented with various commercially available operating systems or combinations of operating systems.

A user can enter commands and information into the computer 1002 through one or more wired/wireless input devices, e.g., a keyboard 1038 and a pointing device, such as a mouse 1040. Other input devices (not shown) can include a microphone, an IR remote control, a joystick, a game pad, a stylus pen, touch screen, or the like. These and other input devices are often connected to the processing unit 1004 through an input device interface 1042 that is coupled to the system bus 1008, but can be connected by other interfaces, such as a parallel port, an IEEE 1394 serial port, a game port, a USB port, an IR interface, etc.

A monitor 1044 or other type of display device is also connected to the system bus 1008 via an interface, such as a video adapter 1046. In addition to the monitor 1044, a computer typically includes other peripheral output devices (not shown), such as speakers, printers, etc.

The computer 1002 can operate in a networked environment using logical connections via wired and/or wireless communications to one or more remote computers, such as a remote computer(s) 1048. The remote computer(s) 1048 can be a workstation, a server computer, a router, a personal computer, portable computer, microprocessor-based entertainment appliance, a peer device or other common network node, and typically includes many or all of the elements described relative to the computer 1002, although, for purposes of brevity, only a memory/storage device 1050 is illustrated. The logical connections depicted include wired/wireless connectivity to a local area network 1052 and/or larger networks, e.g., a wide area network 1054. Such local area network and wide area network networking environments are commonplace in offices and companies, and facilitate enterprise-wide computer networks, such as intranets, all of which can connect to a global communications network, e.g., the Internet.

When used in a local area network networking environment, the computer 1002 is connected to the local network 1052 through a wired and/or wireless communication network interface or adapter 1056. The adapter 1056 can facilitate wired or wireless communication to the local area network 1052, which can also include a wireless access point disposed thereon for communicating with the wireless adapter 1056.

When used in a wide area network environment, the computer 1002 can include a modem 1058, or is connected to a communications server on the wide area network 1054, or has other means for establishing communications over the wide area network 1354, such as by way of the Internet. The modem 1058, which can be internal or external and a wired or wireless device, is connected to the system bus 1008 via the serial port interface 1042. In a networked environment, program modules depicted relative to the computer 1002, or portions thereof, can be stored in the remote memory/storage device 1050. It is noted that the network connections shown are example and other means of establishing a communications link between the computers can be used.

The computer 1002 is operable to communicate with any wireless devices or entities operatively disposed in wireless communication, e.g., a printer, scanner, desktop and/or portable computer, portable data assistant, communications satellite, any piece of equipment or location associated with a wirelessly detectable tag (e.g., a kiosk, news stand, restroom), and telephone. In an example embodiment, wireless communications can be facilitated, for example, using Wi-Fi, Bluetooth™, Zigbee, and other 802.XX wireless technologies. Thus, the communication can be a predefined structure as with a conventional network or simply an ad hoc communication between at least two devices.

Wi-Fi, or Wireless Fidelity, allows connection to the Internet from a couch at home, a bed in a hotel room, or a conference room at work, without wires. Wi-Fi is a wireless technology similar to that used in a cell phone that enables such devices, e.g., computers, to send and receive data indoors and out; anywhere within the range of a base station. Wi-Fi networks use radio technologies called IEEE 802.11 (a, b, g, n, etc.) to provide secure, reliable, fast wireless connectivity. A Wi-Fi network can be used to connect computers to each other, to the Internet, and to wired networks (which use IEEE 802.3 or Ethernet). Wi-Fi networks can operate in the unlicensed 2.4 and 5 GHz radio bands, at an 12 Mbps (802.11a), 54 Mbps (802.11b), or 150 Mbps (802.11n) data rate, for example, or with products that contain both bands (dual band), so the networks can provide real-world performance similar to wired Ethernet networks used in many homes and/or offices.

As it employed in the subject specification, the term “processor” can refer to substantially any computing processing unit or device comprising, but not limited to comprising, single-core processors; single-processors with software multithread execution capability; multi-core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Processors can exploit nano-scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. A processor may also be implemented as a combination of computing processing units.

In the subject specification, terms such as “data store,” data storage,” “database,” and substantially any other information storage component relevant to operation and functionality of a component, refer to “memory components,” or entities embodied in a “memory” or components comprising the memory. It is noted that the memory components, or computer-readable storage media, described herein can be either volatile memory(s) or nonvolatile memory(s), or can include both volatile and nonvolatile memory(s).

By way of illustration, and not limitation, nonvolatile memory(s) can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), or flash memory. Volatile memory(s) can include random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct Rambus RAM (DRRAM). Additionally, the disclosed memory components of systems or methods herein are intended to comprise, without being limited to comprising, these and any other suitable types of memory.

As used in this application, the terms “component,” “module,” “system,” “interface,” “platform,” “service,” “framework,” “connector,” “controller,” or the like are generally intended to refer to a computer-related entity, either hardware, a combination of hardware and software, software, or software in execution or an entity related to an operational machine with one or more specific functionalities. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a controller and the controller can be a component. One or more components may reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. As another example, an interface can include I/O components as well as associated processor, application, and/or API components.

Further, the various embodiments can be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof to control a computer to implement one or more aspects of the disclosed subject matter. An article of manufacture can encompass a computer program accessible from any computer-readable device or computer-readable storage/communications media. For example, computer readable storage media can include but are not limited to magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips . . . ), optical disks (e.g., compact disk (CD), digital versatile disk (DVD) . . . ), smart cards, and flash memory devices (e.g., card, stick, key drive . . . ). Of course, those skilled in the art will recognize many modifications can be made to this configuration without departing from the scope or spirit of the various embodiments.

What has been described above includes examples of the present specification. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present specification, but one of ordinary skill in the art may recognize that many further combinations and permutations of the present specification are possible. Accordingly, the present specification is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term “includes” is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim. 

What is claimed is:
 1. A system, comprising: a processor; and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising: initializing a system parameter; randomly generating a private key based on Diffie-Hellman key exchange with a message recipient device; generating a base matrix pair as a function of the private key that is synchronized with another base matrix pair of the message recipient device: determining a threshold vector using the system parameter and the private key resulting in a synchronized threshold vector with the message recipient device; and encrypting a communication based on the synchronized threshold vector and the synchronized base matrix pair.
 2. The system of claim 1, wherein the determining the threshold vector is based on a summation of a result of a set of functions of the synchronized base matrix pair and a public key.
 3. The system of claim 2, wherein the set of functions of the base matrix pair and the public key are based on a clipped Hopfield neural network.
 4. The system of claim 2, wherein the function of the base matrix pair and the public key is multivariate.
 5. The system of claim 1, wherein the system parameter comprises a number of inputs for an artificial neuron.
 6. The system of claim 1, wherein the system parameters comprises an iteration time.
 7. The system of claim 1, wherein the base matrix pair is based on a communication received from a message recipient device.
 8. The system of claim 7, wherein the communication comprises a unit array based on a number of inputs for an artificial neuron system parameter.
 9. The system of claim 1, wherein the determining the threshold vector comprises determining a mask vector based on a set of randomly generated sets of vectors that have a random length.
 10. A method, comprising: determining, by a system comprising a processor, a set of system parameters; generating a random private key based on a Diffie-Hellman key exchange program with a device associated with a message recipient; generating a base matrix pair as a function of the private key that is synchronized with another base matrix pair of the message recipient; synchronizing a threshold vector with another threshold vector of the message recipient using a system parameter of the set of system parameters and the private key; and encrypting a communication using the threshold vector and the synchronized base matrix pair.
 11. The method of claim 10, wherein the synchronizing the threshold vector is based on a summation of a result of a set of functions of the base matrix pair and a public key.
 12. The method of claim 11, wherein the set of functions of the synchronized base matrix pair and the public key are based on a clipped Hopfield neural network.
 13. The method of claim 11, wherein the set of functions of the base matrix pair and the public key are multivariate.
 14. The method of claim 10, wherein the set of system parameters comprises an iteration time.
 15. The method of claim 10, wherein the set of system parameters comprises a number of inputs for an artificial neuron.
 16. The method of claim 10, wherein the communication comprises a unit array based on a number of inputs for an artificial neuron system parameter.
 17. The method of claim 10, further comprising: generating, by the system, a threshold vector comprising determining a mask vector based on a set of randomly generated sets of vectors that have a random length.
 18. The method of claim 10, wherein the synchronized base matrix pair is based on a communication received from the device associated with the message recipient.
 19. A system, comprising: a processor; and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising: initializing a system parameter; randomly generating a private key based on a Diffie-Hellman key exchange with a sending device; generating a base matrix pair as a function of the private keys, wherein the base matrix pair is synchronized with the sending device: determining a threshold vector using the system parameter and the private key; and decrypting a received message based on the threshold vector and the base matrix pair.
 20. The system of claim 19, wherein the base matrix pair is based on a communication received from a device associated with a sending device. 